Under a typical computer system architecture, a memory controller controls access to the system memory during read and write cycles. For accessing the system memory, the memory controller processes read and write requests generated by a central processor unit (CPU), requesting data to be read from or written into a particular memory address. Upon receipt of the CPU requests, the memory controller initiates corresponding read or write cycles over a data bus, for accessing the addressed memory locations. The rate by which data is transferred, i.e., the data throughput, during each memory cycle is dependent on the bus speed as well as the width of the system's data bus and the length of a memory position, which is defined in terms of data bits, for example, 8-bit, 16-bit, or 32-bit, etc.
Each memory cycle, read or write, expends a predefined number of clock cycles, which is primarily dependent on the speed by which data can be accessed from the memory. Because the performance of a computer system is highly dependent on the data throughput, it is necessary to maximize the data transfer rate over the data bus, ideally, making it reach the full system clock speed. In addition, various techniques have been devised to increase the data throughput by minimizing the time required to access the system memory. For example, under a scheme known as data interleaving, the system memory is divided into a number of DSUs, with each DSU being addressable on a corresponding separate physical address. When accessing data, either reading or writing data, the memory bus is switched from one DSU to another after the memory controller maps the logical memory address to the physical address. In this way, data may be written to a physical address on one DSU without completing a previous write request to a physical address on another DSU.
When reading or writing data, the data bus is driven by corresponding read and write drivers. For example, the memory controller may drive the data bus during the write cycles, and a Data Storage Unit (DSU) may drive the bus during the read cycles. Physical property of the data bus, however, requires the elapse of certain amount of bus settlement time, before valid data may be presented on the data bus. In a system that utilizes a high speed data bus, the initial requirement for the elapse of the bus settlement time may prevent operating the data bus at full speed, when the bus drivers are switched. It is, however, desired to provide memory access at full speed even when switching from one driver to another.